EDN

Mixed language suits complex SoCs

n the past, developers designed ASICs to solve specific problems using pure hardware solutions. More recently, higher levels of integration have produced complete system-on-chip (SoC) designs that now ...
Electronic Design

EDA Update: Mixed HDL/C-Language Design For FPGAs

Mixed HDL/C-Language design for FPGAs recently debuted, courtesy of Aldec Inc. and Celoxica Ltd. The Active-HDL+C integrated FPGA design environment combines Aldec's Active-HDL design entry and ...
Business Wire

Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
EDN

HDL generation language adds open-source license

SANTA CRUZ, Calif. — Confluence, a declarative programming language that generates RTL code, C language models, and formal verification models, is now available under the GNU General Public License.
Business Wire

Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...
Design-Reuse

A Step By Step Methodical Approach for Efficient Mixed-Language IP Integration

--The wide variety of design languages available today poses a significant barrier to IP reuse. SystemC, SystemVerilog, and conventional HDL languages have unique strengths which make them more ...
Design-Reuse

State of RTL based design - is it time to move beyond?

Synopsys is celebrating its 25th anniversary this year. This also means that availability of commercial logic synthesis is turning 25 years old. This paper looks at the history of logic ...