This repository contains two implementations of a phase-locked loop (PLL) on a FPGA (field-programmable gate array). We use the Labview graphical programming environment to generate FPGA binary code ...
Real-time testing and simulation of open- and closed-loop radio frequency (RF) systems for signal generation, signal analysis and digital signal processing require deterministic, low-latency, ...
Real-time testing and simulation of open- and closed-loop radio frequency (RF) systems for signal generation, signal analysis and digital signal processing require deterministic, low-latency, ...
This project implements a user-configurable double pulse generator using an FPGA (Cyclone III on DE0 board) and a LabVIEW user interface. The system allows the user to set timing parameters (High1 ...
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