Zeno’s one-transistor Bi-SRAM uses a single transistor and is ~5× smaller than a conventional SRAM — which uses six-transistor bitcells (6T-SRAM) — at the same technology node One way to look at a ...

TOKYO — Renesas Technology Corp. has developed an SRAM memory cell that it claims can reduce soft error rates at the same time as reducing cell size and power ...

“AI chips commonly employ SRAM memory as buffers for their reliability and speed, which contribute to high performance. However, SRAM is expensive and demands significant area and energy consumption.

A new technical paper titled “Enabling static random-access memory cell scaling with monolithic 3D integration of 2D field-effect transistors” was published by researchers at The Pennsylvania State ...