IEEE

Leakage power analysis of 25-nm double-gate CMOS devices and circuits

Abstract: Leakage power and input pattern dependence of leakage for extremely scaled (L/sub eff/=25nm) double-gate (DG) circuits are analyzed, compared with those of conventional bulk-Si counterpart.
GitHub

Sj1928/cmos-basics-LTSPICE-VLSI

Basic CMOS Circuits Simulated with LTspice This repository contains simulations of basic CMOS (Complementary Metal-Oxide-Semiconductor) logic circuits using LTspice. It includes the implementation of ...
EDN

Detect wire breaks with unusual CMOS gate circuit

CMOS devices have large input impedance with input currents on the order of 0.01nA. Adding feedback circuitry can result in a latch-like device that can be used to store bits, and also operate in a ...
IEEE

High Speed Low Gate Leakage Large Capacitive-Load Driver Circuits for Low-Voltage CMOS

Abstract: In this work, a high-speed full swing driver for large capacitive-loads for low-voltage CMOS applications is presented. The driver which has multi-path for driving the load has a low gate ...
EDN

Driving CMOS totem poles with logic signals, AC coupling, and grounded gates

Despite massive, large-scale integration being ubiquitous in contemporary electronic design, discrete MOSFETs in the classic CMOS totem pole topology are still sometimes indispensable. This makes tips ...