GitHub

DE10_LITE_Golden_Top.v

bcd_adder_top_level_alt bcda (.A(SW[7:4]), .B(SW[3:0]), .C_in(SW[8]), .HEX0(HEX0), .HEX1(HEX1)); bcd2_to_seg7 A (.BCD(SW[7:4]), .HEX0(HEX4), .HEX1(HEX5)); bcd2_to ...
GitHub

HanaEldemery/4-Bit-Adder-with-BCD-Display-using-VHDL-and-FPGA

I designed a 4-bit adder using the DE10-lite FPGA board. The core of this project was to implement an adder circuit that could handle 4-bit binary numbers. To achieve this, I utilized 8 switches on ...
IEEE

Energy-efficient implementation of BCD to Excess-3 code converter for nano-communication using QCA technology

Abstract: Code converters are essential in digital nano communication; therefore, a low-complexity optimal QCA layout for a BCD to Excess-3 code converter has been proposed in this paper. A QCA ...
IEEE

Analysis and design of reversible excess-3 adder and subtractor

Abstract: Power is one of the most important design parameter after speed, in integrated circuit. One of the basic fundamental component in such circuit is adder and subtractor. In order to optimize ...