A layout-dependent circuit-design model from Toshiba helps boost gate density and improve cost-performance in next-generation 45-nm CMOS technology. More specifically, 45-nm CMOS gate density can be 2 ...

At the IEEE International Electron Devices Meeting being held this week, Leuven, Belgium-based nanotechnology research center IMEC is reporting significant progress in improving the performance of ...

CMOS devices have large input impedance with input currents on the order of 0.01nA. Adding feedback circuitry can result in a latch-like device that can be used to store bits, and also operate in a ...

Density and speed of IC’s have increased exponentially for several decades, following a trend described by Moore’s Law. While it is accepted that this exponential improvement trend will end, it is ...

Any typical digital design style with CMOS uses complementary pairs of p-type and n-type MOSFETs for logic functions implementation. Naturally, CMOS always ought to provide INVERTED outputs like ...

IMEC, the Belgium-based nanotechnology research center, announced at this week's VLSI Symposium that it has improved the performance of its planar CMOS using hafnium-based, high-k dielectrics and ...

If your introduction to digital electronics came more years ago than you’d care to mention, the chances are you did so with 5V TTL logic. Above 2V but usually pretty close to 5V is a logic 1, below ...

Taking the final step in the quest for dual metal gates, SEMATECH engineers have demonstrated high-k/metal gate stacks that were used to build high-performance nMOS and pMOS transistors in a CMOS ...

Electric gate-controlled exchange-bias effect in van der Waals heterostructures has been has observed for the first time, according to RMIT University in Australia, which describes the effect as “a ...