EDN

Optimizing DSP functions in advanced FPGA architectures

Although FFT and FIR filters may seem complex, in reality they use simple add/subtract/multiply operations. So how can these arithmetic modules, along with shift and pipeline registers in modern FPGAs ...
Electronics Weekly

DSP versus FPGA

In considering the design option for DSP vs. FPGA it is helpful to compare both architectures in a FIR filter application, writes Reg Zatrepalek One of the most widely used digital signal-processing ...
GitHub

3b3al-MV/Spartan6-FPGA-DSP48A1-Slice-Design

This repository contains a Verilog implementation of the Spartan-6 Field-Programmable Gate Array (FPGA) DSP48A1 Slice and a corresponding testbench for verification with a do file to speed up the ...
IEEE

Feasibility of fixed-point transversal adaptive filters in FPGA devices with embedded DSP blocks

Abstract: Transversal adaptive filters for digital signal processing have traditionally been implemented into DSP processors due to their ability to perform fast floating-point arithmetic. However, ...
EDN

Product how-to: DSP/FPGA platform for video surveillance

Surveillance applications are constantly evolving, adding new features like analytics, image stabilization, image recognition, motion estimation, and target tracking. The features demand improved ...
Electronic Design

PCs Bridge The Gap Between DSP And FPGA Designers

Typically, DSP designers are unfamiliar with FPGA design tools, and FPGA designers are unfamiliar with DSP algorithms. But when Sandia National Laboratories needed to replace an analog implementation ...
Design-Reuse

Flex Logix Extends Embedded FPGA-in-SoC Architecture with New Block RAM and DSP Cores

Santa Clara, CA -- September 17, 2015 -- Flex Logix, innovative developer of FPGA-in-SoC technology, today announced the extension of its core FPGA logic architecture to include Block RAM (BRAM) and ...
Electronic Design

FPGA Flexibility Lights A Fire Under DSPs

Many computationally intensive DSP applications can take advantage of a specialized compute array tuned for the task at hand. This method runs rings around a commercial DSP solution. Or, such an array ...
GitHub

Question about DSP, way to use it with pre-adders and cascading as single big block, and cascading those

Came here because looking for alternative for GOWIN FPGA Designer, because it lack in DSP full potential use. Short about use case: implementing 1d signal filter - Gaussian blur (it's center ...