EDN

Mentor Unveils FPGA Design-Flow Plans

WILSONVILLE, Ore.–May 19, 2003–Mentor Graphics Corporation announced a comprehensive field-programmable gate array (FPGA) design flow that expands traditional FPGA tools with new technologies to ...
Embedded

CPU plus FPGA design flow for software developers: A new tangible reality

Recently, Brian Bailey organized a round table that resulted in a two-part article called Supporting CPUs Plus FPGAs. The experts discussed the evolving reality of systems design based on FPGAs and ...
EDN

Advanced FPGA Design Flow and Real-Time Measurement Solution

Agilent Technologies today announced that the Agilent EEsof EDA W1462 SystemVue FPGA Architect now supports on-board FPGA design and simulation with the Agilent M9703A AXIe wideband digital ...
Electronic Design

Agilent FPGA design flow supports AXIe digitizer

June 23, 2014. Agilent Technologies Inc. has announced that the Agilent EEsof EDA W1462 SystemVue FPGA Architect now supports on-board FPGA design and simulation with the Agilent M9703A AXIe wideband ...
Design-Reuse

FPGA synthesis can be a leverage point in your design flow

FPGA design starts are on the rise due to the lower startup costs and re-programmability that FPGA devices can provide. However, large, complex FPGA devices pose significant challenges to an FPGA ...
Electronic Design

Xilinx And Synopsys Collaborate On Tool Flow For Platform FPGAs

Time-saving verification tools have been added to an advanced tool flow for high-end FPGA design. The flow, a collaboration between Xilinx Inc. of San Jose and Synopsys Inc. of Mountain View, Calif., ...
Semiconductor Engineering

Why Your FPGA Synthesis Flow Requires Verification

When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL ...
Electronics Weekly

FPGA design at a logical level

Xilinx is working with AccelChip to offer a method by which chips can be designed at a logical level, without having to use programming languages such as C. Based on The MathWorks’ MATLAB/Simulink ...
Design-Reuse

QuickPlay Extends its Leadership in Software Defined FPGA Development Flow with the Release of Version 2.0

PLDA today announced the release of version 2.0 of its QuickPlay development platform. QuickPlay is a software defined FPGA development environment that enables developers with little to no FPGA ...
Embedded

The four Rs of efficient system design

New design languages and new chips and systems mean a whole new set of design gotchas for today's developers. Once-simple tasks become difficult and, thankfully, once-difficult tasks become easy. This ...