IEEE

Design of high speed DDR SDRAM controller with less logic utilization

Abstract: This paper focuses on controlling synchronous dynamic random access memory (SDRAM) higher data transfer rates when multiple locations in internal memory array are accessed successively. The ...
GitHub

zynq_ddr_design_ex

simulation setup (written in verilog) to simulate the signals of an AXI master burst IPIF and user logic (designed in vivado design suite aimed at zynq devices based xilinx FPGAs) NOTE - this work is ...
GitHub

simulation setup (written in verilog) to simulate the signals of an AXI master burst IPIF and user logic (designed in vivado design suite aimed at zynq devices based xilinx FPGAs)

NOTE - this work is based on the work released by TU-Kaiserslautern under the GPL licanse. For more information, please visit the following link. https://ems.eit.uni ...
EDN

Tektronix Introduces Most Comprehensive Test Set for Next Generation DDR3 Memory

Comprehensive Test from Analog to Digital Validation for All DDR Versions; New TLA7BB4 Module Provides the Only Logic Analysis Solution to Address All DDR Speeds BEAVERTON , Ore. , March 17, 2008 – ...
Electronic Design

High-Speed DDR3 Interposer Outfits Popular Logic Analyzers

Heralded as the fastest DDR3 interposer for use with Tektronix TLA7000 series logic analyzers, the FS2355 DDR3 1333 interposer preprocessor for next-generation DDR SDRAM buses promises to enhance the ...
EDN

Tektronix delivers complete DDR memory test bench

Beaverton, Ore. — Tektronix, Inc. has released a comprehensive test tool set for DDR2 and new DDR3 SDRAM technology, developed to deliver higher performance data rates. The Tektronix DDR test solution ...
Design-Reuse

Industry Collaboration For DDR Memory System Development Joined by LSI and STMicroelectronics

Expanded Working Group to Deliver Next Version of DDR PHY Specification Minimizing Design and Integration Cost Benefits with Reusable IP SUNNYVALE, Calif., July 23, 2008 – Denali Software, Inc., ...