├── DDCO_Mini_Project_Report.md # Academic report (5 pages) ├── README.md # This file ├── src/ # Source Verilog files │ ├── control_unit.v # FSM-based Control Unit (main module) │ ├── alu.v # ...
The Altera JESD204B IP core is a high-speed point-to-point serial interface for digital-to-analog (DAC) or analog-to-digital (ADC) converters to transfer data to or from the FPGA devices. The JESD204B ...
vhdtdtfi -lang verilog -prj RISC_Processor -o "D:/Uni/Term 7/Architecture Lab/CPU/RISC_Processor/Control_Unit.tfi" -lib work "D:/Uni/Term 7/Architecture Lab/CPU/RISC ...
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