Electronic Design

Find the Fastest Route to Portable Stimulus Tests with SystemVerilog

Download this article in PDF format. The Portable Stimulus Specification (PSS) is all about reusing commonly used test atoms to create new scenarios more quickly. It saves us from wasting precious ...
EDN

Startup embeds RTL Verilog in C++ class library

Santa Cruz, Calif. — Promising a low-cost approach to chip design, startup Tenko Technologies Inc. (San Jose, Calif.) is going into beta test with CvSDL, a C++ class library for design and ...
Semiconductor Engineering

Updated UVM Cookbook Supports IEEE 1800.2 Standard And Emulation

I’m happy to announce that we at Mentor have just released a fully-updated version of our popular UVM Cookbook, which is available online here. Cookbook Overview Diagram The Universal Verification ...
Electronic Design

SystemVerilog Gains A Foothold In Verification

Indeed, designers have embraced SystemVerilog—it's by far the fastest growing design/verification language in the world today (Fig. 1). "The ability to do assertions is significantly improved in ...
Design-Reuse

SystemC library supporting OVM compliant verification methodology

This paper describes the SystemC library that support Open Verification Methodology as defined by Mentor Graphics and Cadence with their SystemVerilog–based approach. Application of the library in ...
Semiconductor Engineering

Making Declarative Modeling Modular: Portable Stimulus Introduces Dynamic Constraints

Naturally, Accellera’s Portable Stimulus Standard (PSS) supports the powerful capabilities of advanced verification techniques that are well-known in the industry today, including object-oriented ...
Design-Reuse

OKI Turns to Cadence and the Open Verification Methodology (OVM) to Speed Product Development

OVM Enables OKI to Improve Verification IP Integration and Compress Testbench Development by 30% SAN JOSE, Calif. -- 29 Jul 2008-- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global ...