IEEE

Synthesis of VHDL code for FPGA design flow using Xilinx PlanAhead tool

Abstract: This paper addresses a synthesis process of VHDL code for FPGA design flow using Xilinx PlanAhead tool. This tool provide a low power profile, more hard IP functionality, create a global ...
IEEE

Development of a reliable GUI for DiaHDL: A web-based VHDL code generator

Abstract: The VHDL generator tools aim is to translate designed component diagram to synthesizable VHDL code. The tools is web based, its provides a graphical user interface that allows the user to ...
GitHub

satunheim/ConvCoTM-FPGA-28x28

This repository includes VHDL code for an FPGA implementation of a Convolutional Coalesced Tsetlin Machine (ConvCoTM)-based Image Classification Accelerator with On-Device Training. The design has ...