GitHub

ParsaAzari/Full-Adder-Gate

This repository contains the implementation of a 1-bit full adder in VHDL, a fundamental building block in digital electronics used to perform binary addition. The full adder adds two input binary ...
GitHub

HanaEldemery/4-Bit-Adder-with-BCD-Display-using-VHDL-and-FPGA

I designed a 4-bit adder using the DE10-lite FPGA board. The core of this project was to implement an adder circuit that could handle 4-bit binary numbers. To achieve this, I utilized 8 switches on ...
EDN

VHDL 101 – From Logic Gates to Adders

VHDL is all about creating logic. As a descriptive language, all the HDL languages bring something unique to programming – making true parallel logic circuit. As we take baby steps into VHDL, we will ...
TechRepublic

32 Bit Parallel Multiplier Using VHDL

In this paper, design of 32-bit parallel multiplier is presented, by introducing Carry Save Adder (CSA) in partial product lines. The multiplier given in this paper is modeled using VHDL (Very High ...
EDN

Control Synthesis Output with Combinatorial Logic in Procedural Code

While it is tempting to write RTL and let the synthesis tool take over, this isn’t the best way to get the results we want. In this article, we’ll learn how to create complex combinatorial code in ...
TechRepublic

VHDL Implementation of 8-Bit ALU

In this paper VHDL implementation of 8-bit Arithmetic Logic Unit (ALU) is presented. The design was implemented using VHDL Xilinx Synthesis tool ISE 13.1 and targeted for Spartan device. ALU was ...
IEEE

Improved Decimal Rounding Module based on Compound Adder

Abstract: A new approach and architecture have been presented in this paper to efficiently merge the decimal rounding stage according to the IEEE 754-2008 standard based on the compound adder. This ...