Electronic Design

ASIC Handoff Gets Physical As Front And Back Ends Converge

True or false: ASIC design follows a very straightforward path that begins with high-level architectural definition. It proceeds through RTL design and preliminary floorplanning. After synthesis, the ...
Design-Reuse

Opto-electronics -> Architectural synthesis provides flexibilty in optical network design

Circuit design for high-speed networks is becoming more complex as companies compete to deliver hardware that can deal with the increasing volumes of data generated by rising Internet usage. Many are ...
Semiconductor Engineering

Why Your FPGA Synthesis Flow Requires Verification

When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL ...
Semiconductor Engineering

The Rise and Fall of Synthesis Bugs in Safety-Critical FPGAs

How to create an implementation signoff flow proving that the final FPGA netlist is functionally equivalent to the RTL model. For standards IEC 61508 / ISO 26262 / EN 50128 / DO-254. FPGAs are the ...
Electronic Design

Design-For-Test Tool Eliminates Need For Gate-Level Scan

If there's a truism in design debug and test, it's that the earlier you can find a bug, the less costly it is to fix. Thus, finding bugs at RTL is far preferable to finding them after synthesis. With ...