GitHub

Bhagyashree-nyamaji5/3to8-decoder

This project involves the design and verification of a 3-to-8 decoder using Verilog HDL. A 3-to-8 decoder is a combinational circuit that takes a 3-bit binary input and activates one of the 8 output ...
IEEE

Implementation of Combinational Logic for Polar Decoder

Abstract: Error free communication is possible due to channel coding. Polar code has been identified by control channel code for 5G wireless communication. In this ...
IEEE

Timing analysis of combinational circuits using Weights Binary Decision Diagram (WBDD)

Abstract: Weights Binary Decision Diagram (WBDD) based timing analysis of combinational circuit is proposed. Here we express the combinational circuit as a directed graph. We compute and store the ...